A Subthreshold Bootstrapped SAPTL-Based Adder Design
This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amp...
Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
MDPI AG
2019-10-01
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Series: | Electronics |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9292/8/10/1161 |