A Subthreshold Bootstrapped SAPTL-Based Adder Design

A Subthreshold Bootstrapped SAPTL-Based Adder Design

This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amp...

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Bibliographic Details
Main Authors: Qi Zhang, Yuping Wu, Lan Chen
Format: Article
Language:English
Published: MDPI AG 2019-10-01
Series:Electronics
Subjects:
ultra-low power
subthreshold circuit
bootstrapped circuit
saptl
adder
energy efficiency
robustness
process variation
Online Access:https://www.mdpi.com/2079-9292/8/10/1161

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https://www.mdpi.com/2079-9292/8/10/1161

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