Synchronous Counters Implemented in the PLD Devices
The implementability of synchronous counters in the Programmable Logic Devices (PLD) is discussed in this paper. The most commonly used counters are analysed from this point of view. The expressions for their individual bits are given and the number of product terms is derived to allow to estimate t...
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| Format: | Article |
| Language: | English |
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Spolecnost pro radioelektronicke inzenyrstvi
1999-04-01
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| Series: | Radioengineering |
| Online Access: | http://www.radioeng.cz/fulltexts/1999/99_01_03.pdf |