Anti-conflict design for reading and writing of DDR3 six channels based on FPGA

Anti-conflict design for reading and writing of DDR3 six channels based on FPGA

In order to solve the problem of data conflict of reading and writing when multiple channels access DDR3 at the same time in the acceleration processing of futures market data, an anti-conflict design for reading and writing of DDR3 six channels based on FPGA is implemented and the requirement of mu...

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Bibliographic Details
Main Authors: Zhang Fengqi, Zhang Yanbin, Wang Zhongyong
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2018-07-01
Series:Dianzi Jishu Yingyong
Subjects:
multiple channels
anti-conflict
DDR3
FPGA
Online Access:http://www.chinaaet.com/article/3000086048

Internet

http://www.chinaaet.com/article/3000086048

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