Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to...

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Bibliographic Details
Main Authors: Rafał Kiełbik, Kamil Rudnicki, Zbigniew Mudza, Jarosław Jung
Format: Article
Language:English
Published: MDPI AG 2020-09-01
Series:Electronics
Subjects:
computer aided engineering
design automation
high level synthesis
high performance computing
programmable logic arrays
reconfigurable architectures
Online Access:https://www.mdpi.com/2079-9292/9/9/1482

Internet

https://www.mdpi.com/2079-9292/9/9/1482

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