Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

In the new energy grid-connected power generation system, accurately extracting the grid synchronization signals such as the frequency, phase and amplitude of the grid voltage is the basis for effective control. Aiming at the requirements for detecting grid synchronization signals under unbalanced,...

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Bibliographic Details
Main Authors: Nanmu Hui, Yingying Feng, Xiaowei Han
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Dual second-order complex coefficient filter (DSOCCF)
harmonic
phase-locked loop (PLL)
dc offset
moving average filter (MAF)
Online Access:https://ieeexplore.ieee.org/document/8950104/

Internet

https://ieeexplore.ieee.org/document/8950104/

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