Low‐power heterogeneous uncore architecture for future 3D chip‐multiprocessors

Low‐power heterogeneous uncore architecture for future 3D chip‐multiprocessors

Uncore components such as on‐chip memory systems and on‐chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next‐generation analytical models for future chip‐multiprocessors (CMPs) that simultaneously consider the impacts of the power co...

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Bibliographic Details
Main Authors: Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy, Mohammad Reza Jahed‐Motlagh, Farah Mohammadi
Format: Article
Language:English
Published: Electronics and Telecommunications Research Institute (ETRI) 2018-10-01
Series:ETRI Journal
Subjects:
embedded chip‐multiprocessor
heterogeneous memory system
nonvolatile memory
optimal placement
through silicon via
uncore
Online Access:https://doi.org/10.4218/etrij.2017-0095

Internet

https://doi.org/10.4218/etrij.2017-0095

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