RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

Redundant number systems (RNS) are a well-known technique to speed up arithmetic circuits. However, in a complete CPU, arithmetic circuits using RNS were only included on subcircuit level e.g. inside the Arithmetic Logic Unit (ALU) for realization of the division. Still, extending this approach to c...

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Bibliographic Details
Main Authors: Marc Reichenbach, Johannes Knodtel, Sebastian Rachuj, Dietmar Fey
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Arithmetic and logic units
processor architectures
RISC
ternary arithmetic
Online Access:https://ieeexplore.ieee.org/document/9366755/

Internet

https://ieeexplore.ieee.org/document/9366755/

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