RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems
Redundant number systems (RNS) are a well-known technique to speed up arithmetic circuits. However, in a complete CPU, arithmetic circuits using RNS were only included on subcircuit level e.g. inside the Arithmetic Logic Unit (ALU) for realization of the division. Still, extending this approach to c...
Main Authors: | Marc Reichenbach, Johannes Knodtel, Sebastian Rachuj, Dietmar Fey |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2021-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9366755/ |
Similar Items
-
Risco : microprocessador RISC CMOS de 32 bits
by: Junqueira, Alexandre Ambrozi
Published: (2010) -
Risco : microprocessador RISC CMOS de 32 bits
by: Junqueira, Alexandre Ambrozi
Published: (2010) -
Risco : microprocessador RISC CMOS de 32 bits
by: Junqueira, Alexandre Ambrozi
Published: (2010) -
A RISC-V Processor Design for Transparent Tracing
by: Iván Gamino del Río, et al.
Published: (2020-11-01) -
The design of scalar AES Instruction Set Extensions for RISC-V
by: Ben Marshall, et al.
Published: (2020-12-01)