A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier

• Main Authors: Aiwen Luo, Fengwei An, Xiangyu Zhang, Hans Jurgen Mattausch
• Format: Article
• Language: English
• Published: IEEE 2019-01-01
• Series: IEEE Access
• Subjects: Hardware architecture; Haar-like feature extraction; support vector machine (SVM); object recognition; high-speed processing; flexible memory allocation
• Online Access: https://ieeexplore.ieee.org/document/8621001/

Significantly improved performance of the various learning algorithms has revived the interest in computer vision for recognition applications during the current decade. This paper reports a vision-based hardware recognition architecture combining the Haar-like feature extraction with the support vector machine (SVM) classification. To support an optimal tradeoff between resource requirements, processing speed, and recognition accuracy, a 12-bit fixed-point computation for block-based feature normalization and a recycling allocation of minimalized memory resources are proposed in this paper. Furthermore, an efficient scale generation of target objects for recognition is enabled by configurable windows with high size flexibility. Additionally, a parallel-partial SVM-classification architecture is developed for improving the recognition speed, by accumulating the partially completed SVM results for multiple windows in parallel. The proposed hardware architecture is verified with an Altera DE4 platform to achieve a high throughput rate of 216 and 70 f/s for XGA (1024×768) and HD (1920×1080) video resolutions, respectively. A recycled memory space of only 193 KB is sufficient for processing high-resolution images up to 2048×2048 pixels during online testing. Using the INRIA person dataset, 89.81% average precision and maximum accuracy of 96.93% for pedestrian recognition are realized. Furthermore, about 99.08% accuracy is achieved for two car recognition tasks using the UIUC dataset (side view of cars) and a frontal car dataset collected by ourselves at Hiroshima University with the proposed hardware-architecture framework.