Multibit non-volatile memory based on WS2 transistor with engineered gate stack
In this work, a prototype of a charge-trapping memory device based on two-dimensional WS2 has been fabricated with an engineered gate stack for multilevel non-volatile memory application. A Si/SiO2/ITO/Al2O3/Ta2O5/Al2O3 stack has been successfully integrated with optimized layer thicknesses for enha...
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
AIP Publishing LLC
2020-12-01
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| Series: | AIP Advances |
| Online Access: | http://dx.doi.org/10.1063/5.0037780 |