| Summary: | This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase. In this design, a comparator circuit with four input terminals was also applied to implement a fully differential capacitive digital-to-analog converter (CDAC). Simultaneously, by employing an area-efficient and low-energy switching scheme for the capacitive digital-to-analog converter, the average switching energy can be reduced significantly. The proposed design also achieved a reduction in the number of the capacitors and the controlled switches compared with those required in the conventional SAR ADC design. A prototype had been designed and implemented using TSMC 90-nm CMOS 1P9M technology. The measurement results showed that differential nonlinearity and integral nonlinearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively. At a sampling rate of 50-MS/s with a single 1.2-V power supply, the power consumption was 664 μW. This design also achieved a signal-to-noise-and-distortion ratio of 57.6 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 5-MHz. The ADC core occupied an active area of 102 × 235 μm<sup>2</sup>.
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