A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme
This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase. In this design, a comparator circuit with four input termin...
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doaj-76249439adb3401ca19012acc06ff7922021-03-30T02:01:13ZengIEEEIEEE Access2169-35362020-01-018282572826610.1109/ACCESS.2020.29716658981911A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching SchemeChi-Chang Lu0https://orcid.org/0000-0002-1575-883XDing-Ke Huang1Department of Electrical Engineering, National Formosa University, Huwei, TaiwanDepartment of Electrical Engineering, National Formosa University, Huwei, TaiwanThis paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase. In this design, a comparator circuit with four input terminals was also applied to implement a fully differential capacitive digital-to-analog converter (CDAC). Simultaneously, by employing an area-efficient and low-energy switching scheme for the capacitive digital-to-analog converter, the average switching energy can be reduced significantly. The proposed design also achieved a reduction in the number of the capacitors and the controlled switches compared with those required in the conventional SAR ADC design. A prototype had been designed and implemented using TSMC 90-nm CMOS 1P9M technology. The measurement results showed that differential nonlinearity and integral nonlinearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively. At a sampling rate of 50-MS/s with a single 1.2-V power supply, the power consumption was 664 μW. This design also achieved a signal-to-noise-and-distortion ratio of 57.6 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 5-MHz. The ADC core occupied an active area of 102 × 235 μm<sup>2</sup>.https://ieeexplore.ieee.org/document/8981911/SAR ADCcapacitive digital-to-analog converterlow-power |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Chi-Chang Lu Ding-Ke Huang |
spellingShingle |
Chi-Chang Lu Ding-Ke Huang A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme IEEE Access SAR ADC capacitive digital-to-analog converter low-power |
author_facet |
Chi-Chang Lu Ding-Ke Huang |
author_sort |
Chi-Chang Lu |
title |
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme |
title_short |
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme |
title_full |
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme |
title_fullStr |
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme |
title_full_unstemmed |
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme |
title_sort |
10-bits 50-ms/s sar adc based on area-efficient and low-energy switching scheme |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2020-01-01 |
description |
This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase. In this design, a comparator circuit with four input terminals was also applied to implement a fully differential capacitive digital-to-analog converter (CDAC). Simultaneously, by employing an area-efficient and low-energy switching scheme for the capacitive digital-to-analog converter, the average switching energy can be reduced significantly. The proposed design also achieved a reduction in the number of the capacitors and the controlled switches compared with those required in the conventional SAR ADC design. A prototype had been designed and implemented using TSMC 90-nm CMOS 1P9M technology. The measurement results showed that differential nonlinearity and integral nonlinearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively. At a sampling rate of 50-MS/s with a single 1.2-V power supply, the power consumption was 664 μW. This design also achieved a signal-to-noise-and-distortion ratio of 57.6 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 5-MHz. The ADC core occupied an active area of 102 × 235 μm<sup>2</sup>. |
topic |
SAR ADC capacitive digital-to-analog converter low-power |
url |
https://ieeexplore.ieee.org/document/8981911/ |
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