Low voltage low power FGMOS based current mirror
This paper presents the comparison of a conventional current mirror with the one utilizing floating gate MOSFET transistors (FGMOS) to achieve low power (LP) and low voltage (LV) design. The device structure has been simulated with 0.1μ CMOS technology and 1.2V voltage supply by using SAED 90nm PDK...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2017-01-01
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| Series: | EPJ Web of Conferences |
| Online Access: | https://doi.org/10.1051/epjconf/201716201048 |