A shared synapse architecture for efficient FPGA implementation of autoencoders.
This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input an...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Public Library of Science (PLoS)
2018-01-01
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| Series: | PLoS ONE |
| Online Access: | http://europepmc.org/articles/PMC5854352?pdf=render |