Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si t...

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Main Authors:	Sang Ho Lee, Won Douk Jang, Young Jun Yoon, Jae Hwa Seo, Hye Jin Mun, Min Su Cho, Jaewon Jang, Jin-Hyuk Bae, In Man Kang
Format:	Article
Language:	English
Published:	IEEE 2021-01-01
Series:	IEEE Access
Subjects:	Polycrystalline silicon one-transistor dynamic random access memory grain boundaries metal–oxide–semiconductor field-effect transistor one transistor dynamic random access memory dualgate
Online Access:	https://ieeexplore.ieee.org/document/9387306/

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spelling	doaj-7d5735572be84b6daa38b0f88d5b79532021-04-05T23:00:52ZengIEEEIEEE Access2169-35362021-01-019502815029010.1109/ACCESS.2021.30689879387306Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its PerformancesSang Ho Lee0https://orcid.org/0000-0002-4954-3861Won Douk Jang1https://orcid.org/0000-0002-1119-3384Young Jun Yoon2Jae Hwa Seo3Hye Jin Mun4https://orcid.org/0000-0003-1949-2466Min Su Cho5https://orcid.org/0000-0002-9372-6796Jaewon Jang6https://orcid.org/0000-0003-1908-0015Jin-Hyuk Bae7https://orcid.org/0000-0003-3217-1309In Man Kang8https://orcid.org/0000-0002-7726-9740School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSamsung Electronics Company Ltd., Hwasung-si, South KoreaKorea Multi-Purpose Accelerator Complex, Korea Atomic Energy Research Institute, Gyeongju, South KoreaSamsung Electronics Company Ltd., Hwasung-si, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaIn this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was utilized within the device because of several advantages, including its low fabrication cost and the feasibility of its use in high-density three-dimensional (3D) memory arrays. An asymmetric dual-gate structure is proposed to perform the write “1” operation and achieve high retention characteristics. The proposed 1T-DRAM cell demonstrates a high sensing margin of <inline-formula> <tex-math notation="LaTeX">$8.73~\mu \text{A} / \mu \text{m}$ </tex-math></inline-formula> and a high retention time of 704.4 ms compared to previously reported 1T-DRAMs, even at a high temperature. In addition, the effect of grain boundaries on the memory performance of the proposed device was investigated, and the results validated the excellent reliability of its retention characteristics even in the presence of grain boundaries (>64 ms at <inline-formula> <tex-math notation="LaTeX">$T =358$ </tex-math></inline-formula> K).https://ieeexplore.ieee.org/document/9387306/Polycrystalline siliconone-transistor dynamic random access memorygrain boundariesmetal–oxide–semiconductor field-effect transistorone transistor dynamic random access memorydualgate
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Sang Ho Lee Won Douk Jang Young Jun Yoon Jae Hwa Seo Hye Jin Mun Min Su Cho Jaewon Jang Jin-Hyuk Bae In Man Kang
spellingShingle	Sang Ho Lee Won Douk Jang Young Jun Yoon Jae Hwa Seo Hye Jin Mun Min Su Cho Jaewon Jang Jin-Hyuk Bae In Man Kang Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances IEEE Access Polycrystalline silicon one-transistor dynamic random access memory grain boundaries metal–oxide–semiconductor field-effect transistor one transistor dynamic random access memory dualgate
author_facet	Sang Ho Lee Won Douk Jang Young Jun Yoon Jae Hwa Seo Hye Jin Mun Min Su Cho Jaewon Jang Jin-Hyuk Bae In Man Kang
author_sort	Sang Ho Lee
title	Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
title_short	Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
title_full	Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
title_fullStr	Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
title_full_unstemmed	Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
title_sort	polycrystalline-silicon-mosfet-based capacitorless dram with grain boundaries and its performances
publisher	IEEE
series	IEEE Access
issn	2169-3536
publishDate	2021-01-01
description	In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was utilized within the device because of several advantages, including its low fabrication cost and the feasibility of its use in high-density three-dimensional (3D) memory arrays. An asymmetric dual-gate structure is proposed to perform the write “1” operation and achieve high retention characteristics. The proposed 1T-DRAM cell demonstrates a high sensing margin of <inline-formula> <tex-math notation="LaTeX">$8.73~\mu \text{A} / \mu \text{m}$ </tex-math></inline-formula> and a high retention time of 704.4 ms compared to previously reported 1T-DRAMs, even at a high temperature. In addition, the effect of grain boundaries on the memory performance of the proposed device was investigated, and the results validated the excellent reliability of its retention characteristics even in the presence of grain boundaries (>64 ms at <inline-formula> <tex-math notation="LaTeX">$T =358$ </tex-math></inline-formula> K).
topic	Polycrystalline silicon one-transistor dynamic random access memory grain boundaries metal–oxide–semiconductor field-effect transistor one transistor dynamic random access memory dualgate
url	https://ieeexplore.ieee.org/document/9387306/
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Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

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