Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement

Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement

To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-c...

Full description

Bibliographic Details
Main Authors: Ming-Hwa Sheu, S M Salahuddin Morsalin, Chang-Ming Tsai, Cheng-Jie Yang, Shih-Chang Hsia, Ya-Hsin Hsueh, Jin-Fa Lin, Chuan-Yu Chang
Format: Article
Language:English
Published: MDPI AG 2021-03-01
Series:Electronics
Subjects:
energy-efficient
local bit-line
static random-access memory
near-threshold operation
low-voltage pre-charged
negative local bit-line
Online Access:https://www.mdpi.com/2079-9292/10/6/685

Internet

https://www.mdpi.com/2079-9292/10/6/685

Similar Items