Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog con...

Full description

Bibliographic Details
Main Authors: Khuram Shehzad, Deeksha Verma, Danial Khan, Qurat Ul Ain, Muhammad Basim, Sung Jin Kim, YoungGun Pu, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee
Format: Article
Language:English
Published: MDPI AG 2020-05-01
Series:Electronics
Subjects:
successive approximation register (SAR) ADC
asynchronous logic
capacitive DAC (CDAC)
adaptive power control (APC)
low power consumption
Online Access:https://www.mdpi.com/2079-9292/9/5/872

Internet

https://www.mdpi.com/2079-9292/9/5/872

Similar Items