Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator
This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog con...
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MDPI AG
2020-05-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/5/872 |
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doaj-8319e21717734244926998cfad4b9a6c2020-11-25T03:17:19ZengMDPI AGElectronics2079-92922020-05-01987287210.3390/electronics9050872Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage GeneratorKhuram Shehzad0Deeksha Verma1Danial Khan2Qurat Ul Ain3Muhammad Basim4Sung Jin Kim5YoungGun Pu6Keum Cheol Hwang7Youngoo Yang8Kang-Yoon Lee9College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, KoreaThis paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CV<sub>REF</sub><sup>2</sup> switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.https://www.mdpi.com/2079-9292/9/5/872successive approximation register (SAR) ADCasynchronous logiccapacitive DAC (CDAC)adaptive power control (APC)low power consumption |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Khuram Shehzad Deeksha Verma Danial Khan Qurat Ul Ain Muhammad Basim Sung Jin Kim YoungGun Pu Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee |
| spellingShingle |
Khuram Shehzad Deeksha Verma Danial Khan Qurat Ul Ain Muhammad Basim Sung Jin Kim YoungGun Pu Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator Electronics successive approximation register (SAR) ADC asynchronous logic capacitive DAC (CDAC) adaptive power control (APC) low power consumption |
| author_facet |
Khuram Shehzad Deeksha Verma Danial Khan Qurat Ul Ain Muhammad Basim Sung Jin Kim YoungGun Pu Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee |
| author_sort |
Khuram Shehzad |
| title |
Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator |
| title_short |
Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator |
| title_full |
Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator |
| title_fullStr |
Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator |
| title_full_unstemmed |
Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator |
| title_sort |
design of a low power 10-b 8-ms/s asynchronous sar adc with on-chip reference voltage generator |
| publisher |
MDPI AG |
| series |
Electronics |
| issn |
2079-9292 |
| publishDate |
2020-05-01 |
| description |
This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CV<sub>REF</sub><sup>2</sup> switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied. |
| topic |
successive approximation register (SAR) ADC asynchronous logic capacitive DAC (CDAC) adaptive power control (APC) low power consumption |
| url |
https://www.mdpi.com/2079-9292/9/5/872 |
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