Low Power Clock Network Design

• Main Authors: Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
• Format: Article
• Language: English
• Published: MDPI AG 2011-05-01
• Series: Journal of Low Power Electronics and Applications
• Subjects: low power; skew; skew variation; crosslinks; mesh; topologies
• Online Access: http://www.mdpi.com/2079-9268/1/1/219/

Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.