30 Gb/s integrated receiver array for parallel optical interconnects

30 Gb/s integrated receiver array for parallel optical interconnects

A 30 Gb/s integrated receiver array for parallel optical interconnects with four channels have been designed and implemented in a 0.13 μm CMOS technology. To achieve small area and low power consumption while maintaining large bandwidth and high gain, the integrated receiver has been implemented wit...

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Bibliographic Details
Main Authors: Nga T.H. Nguyen, Ikechi A. Ukaegbu, Hyo-Hoon Park
Format: Article
Language:English
Published: Wiley 2019-04-01
Series:The Journal of Engineering
Subjects:
low-power electronics
optical interconnections
optical receivers
CMOS integrated circuits
photodiodes
operational amplifiers
integrated receiver array
parallel optical interconnects
low power consumption
capacitive degeneration
inductorless limiting amplifier
optical module
CMOS technology
regulated cascode
transimpedance amplifier
active feedback
negative capacitance
photodiode
figure of merit
size 0.13 mum
size 850.0 nm
voltage 320.0 mV
voltage 1.2 V
bit rate 30 Gbit/s
Online Access:https://digital-library.theiet.org/content/journals/10.1049/joe.2018.5260

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https://digital-library.theiet.org/content/journals/10.1049/joe.2018.5260

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