Ternary and Multi-Bit FIR Filter Area-Performance Tradeoffs in FPGA
In this paper, performance and area of conventional FIR (Finite Impulse Responce) filters versus ternary sigma delta modulated FIR filter is compared in FPGA (Field Programmable Gate Arrays) using VHDL (Verilog Description Language). Two different approaches were designed and synthesized at same spe...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Mehran University of Engineering and Technology
2013-01-01
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| Series: | Mehran University Research Journal of Engineering and Technology |
| Subjects: | |
| Online Access: | http://publications.muet.edu.pk/research_papers/pdf/pdf746.pdf |