Ternary and Multi-Bit FIR Filter Area-Performance Tradeoffs in FPGA

• Main Authors: Khalil-Ur-Rahman Dayo, Tayab Din Memon
• Format: Article
• Language: English
• Published: Mehran University of Engineering and Technology 2013-01-01
• Series: Mehran University Research Journal of Engineering and Technology
• Subjects: Ternary; VHDL; FPGA; Sigma-Delta Modulation
• Online Access: http://publications.muet.edu.pk/research_papers/pdf/pdf746.pdf

In this paper, performance and area of conventional FIR (Finite Impulse Responce) filters versus ternary sigma delta modulated FIR filter is compared in FPGA (Field Programmable Gate Arrays) using VHDL (Verilog Description Language). Two different approaches were designed and synthesized at same spectral performance by obtaining a TIR (Target Impulse Response). Both filters were synthesized on adaptive LUT (Look Up Table) FPGA device in pipelined and non-pipelined modes. It is shown that the Ternary FIR filter occupies approximately the same area as the corresponding multi-bit filter, but for a given specification, the ternary FIR filter has 32% better performance in non-pipelined and 72% in pipelined mode, compared to its equivalent Multi-Bit filter at its optimum 12-bit coefficient quantization. These promising results shows that ternary logic based (i.e. +1,0,-1) filters can be used for huge chip area savings and higher performance.