FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications
This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this p...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Spolecnost pro radioelektronicke inzenyrstvi
2009-09-01
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| Series: | Radioengineering |
| Subjects: | |
| Online Access: | http://www.radioeng.cz/fulltexts/2009/09_03_325_329.pdf |