Technology Independent ASIC Based Time to Digital Converter
This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully au...
Main Authors: | , , , |
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Format: | Article |
Language: | English |
Published: |
IEEE
2020-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9241845/ |