Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor

In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As ea...

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Bibliographic Details
Main Authors: Shunsuke Okura, Masanori Aoki, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino, Kenichiro Ishikawa, Isao Takayanagi
Format: Article
Language:English
Published: MDPI AG 2021-09-01
Series:Sensors
Subjects:
IoT
PUF
Online Access:https://www.mdpi.com/1424-8220/21/18/6079
Description
Summary:In order to realize image information security starting from the data source, challenge–response (CR) device authentication, based on a Physically Unclonable Function (PUF) with a 2 Mpixel CMOS image sensor (CIS), is studied, in which variation of the transistor in the pixel array is utilized. As each CR pair can be used only once to make the CIS PUF resistant to the modeling attack, CR authentication with CIS can be carried out 4050 times, with basic post-processing to generate the PUF ID. If a larger number of authentications is required, advanced post-processing using Lehmer encoding can be utilized to carry out authentication <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>14</mn><mo>,</mo><mn>858</mn></mrow></semantics></math></inline-formula> times. According to the PUF performance evaluation, the authentication error rate is less than <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>0.001</mn></mrow></semantics></math></inline-formula> ppm. Furthermore, the area overhead of the CIS chip for the basic and advanced post-processing is only <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>1</mn><mo>%</mo></mrow></semantics></math></inline-formula> and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>2</mn><mo>%</mo></mrow></semantics></math></inline-formula>, respectively, based on a Verilog HDL model circuit design.
ISSN:1424-8220