The design and debug of timing-clock for JESD204B Subclass1 mode

The design and debug of timing-clock for JESD204B Subclass1 mode

JESD204B protocol is a kind of high-speed series protocol to transmit data between data converter and FPGA or ASIC. Subclass1 is an important mode to implement deterministic latency of JESD204B protocol. This article analyzes the principle and timing requirement of the Subclass1 deterministic latenc...

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Bibliographic Details
Main Authors: Lv Zhipeng, Ma Xiaobing, Yu Weidong
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2018-04-01
Series:Dianzi Jishu Yingyong
Subjects:
JESD204B
Subclass1
deterministic latency
FPGA
timing-clock
Online Access:http://www.chinaaet.com/article/3000080357

Internet

http://www.chinaaet.com/article/3000080357

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