A Single-Amplifier Dual-Residue Pipelined-SAR ADC

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two resid...

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Bibliographic Details
Main Author: Min-Jae Seo
Format: Article
Language:English
Published: MDPI AG 2021-02-01
Series:Electronics
Subjects:
high speed and high resolution
low power
successive-approximation-register (SAR)
analog-to-digital converter (ADC)
pipelined-SAR architecture
open-loop residue amplifier
Online Access:https://www.mdpi.com/2079-9292/10/4/421

Internet

https://www.mdpi.com/2079-9292/10/4/421

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