Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a lar...

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Bibliographic Details
Main Authors: Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jinsu Jeong, Hyeok Yun, Bohyeon Kang, Rock-Hyun Baek
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
5-nm node
source/drain patterning
FinFETs
longitudinal channel stress
ring oscillator
performance-power-area
Online Access:https://ieeexplore.ieee.org/document/8917552/

Internet

https://ieeexplore.ieee.org/document/8917552/

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