Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop
An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-06-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/10/6/411 |