Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment

The use of assertions for monitoring the designer’s intention in hardware description language (HDL) model is gaining popularity as it helps the designer to observe internal errors at the output ports of the device under verification. During verification assertions are synthesised and the generated...

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Main Author: C. U. Ngene
Format: Article
Language:English
Published: University of Maiduguri 2013-08-01
Series:Arid Zone Journal of Engineering, Technology and Environment
Online Access:http://azojete.com.ng/index.php/azojete/article/view/155/130
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spelling doaj-97678a9b30714e17b74552ea0bf2634b2020-11-25T02:19:05ZengUniversity of MaiduguriArid Zone Journal of Engineering, Technology and Environment2545-58182545-58182013-08-0195167Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environmentC. U. Ngene0Department of Computer Engineering University of Maiduguri, Maiduguri, NigeriaThe use of assertions for monitoring the designer’s intention in hardware description language (HDL) model is gaining popularity as it helps the designer to observe internal errors at the output ports of the device under verification. During verification assertions are synthesised and the generated data are represented in a tabular forms. The amount of data generated can be enormous depending on the size of the code and the number of modules that constitute the code. Furthermore, to manually inspect these data and diagnose the module with functional violation is a time consuming process which negatively affects the overall product development time. To locate the module with functional violation within acceptable diagnostic time, the data processing and analysis procedure must be accelerated. In this paper a multi-array processor (hardware accelerator) was designed and implemented in Virtex6 field programmable gate array (FPGA) and it can be integrated into verification environment. The design was captured in very high speed integrated circuit HDL (VHDL). The design was synthesised with Xilinx design suite ISE 13.1 and simulated with Xilinx ISIM. The multi-array processor (MAP) executes three logical operations (AND, OR, XOR) and a one’s compaction operation on array of data in parallel. An improvement in processing and analysis time was recorded as compared to the manual procedure after the multi-array processor was integrated into the verification environment. It was also found that the multi-array processor which was developed as an Intellectual Property (IP) core can also be used in applications where output responses and golden model that are represented in the form of matrices can be compared for searching, recognition and decision-making.http://azojete.com.ng/index.php/azojete/article/view/155/130
collection DOAJ
language English
format Article
sources DOAJ
author C. U. Ngene
spellingShingle C. U. Ngene
Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
Arid Zone Journal of Engineering, Technology and Environment
author_facet C. U. Ngene
author_sort C. U. Ngene
title Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
title_short Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
title_full Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
title_fullStr Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
title_full_unstemmed Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment
title_sort design and implementation of embedded hardware accelerator for diagnosing hdl-code in assertion-based verification environment
publisher University of Maiduguri
series Arid Zone Journal of Engineering, Technology and Environment
issn 2545-5818
2545-5818
publishDate 2013-08-01
description The use of assertions for monitoring the designer’s intention in hardware description language (HDL) model is gaining popularity as it helps the designer to observe internal errors at the output ports of the device under verification. During verification assertions are synthesised and the generated data are represented in a tabular forms. The amount of data generated can be enormous depending on the size of the code and the number of modules that constitute the code. Furthermore, to manually inspect these data and diagnose the module with functional violation is a time consuming process which negatively affects the overall product development time. To locate the module with functional violation within acceptable diagnostic time, the data processing and analysis procedure must be accelerated. In this paper a multi-array processor (hardware accelerator) was designed and implemented in Virtex6 field programmable gate array (FPGA) and it can be integrated into verification environment. The design was captured in very high speed integrated circuit HDL (VHDL). The design was synthesised with Xilinx design suite ISE 13.1 and simulated with Xilinx ISIM. The multi-array processor (MAP) executes three logical operations (AND, OR, XOR) and a one’s compaction operation on array of data in parallel. An improvement in processing and analysis time was recorded as compared to the manual procedure after the multi-array processor was integrated into the verification environment. It was also found that the multi-array processor which was developed as an Intellectual Property (IP) core can also be used in applications where output responses and golden model that are represented in the form of matrices can be compared for searching, recognition and decision-making.
url http://azojete.com.ng/index.php/azojete/article/view/155/130
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