A physical implementation method based on Innovus to improve chip performance
For high-performance chip designs with ever-increasing scale and increasing operating frequency, performance has always been the focus and difficulty of physical design. The buffer is inserted to minimize signal line delay, which optimizes timing and improves performance. The use of Cadence Innovus...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2019-08-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000107391 |