| Summary: | For high-performance chip designs with ever-increasing scale and increasing operating frequency, performance has always been the focus and difficulty of physical design. The buffer is inserted to minimize signal line delay, which optimizes timing and improves performance. The use of Cadence Innovus tools to build physical design flows that reduce deviations between steps is described. At the same time, based on this process, a secondary layout optimization method is proposed. The process and method are verified by a high-performance chip design at 16 nm. The example results show that the design performance is greatly improved, and the timing optimization is 85.07%. The flow and method can effectively improve high performance chip performance.
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