A physical implementation method based on Innovus to improve chip performance

For high-performance chip designs with ever-increasing scale and increasing operating frequency, performance has always been the focus and difficulty of physical design. The buffer is inserted to minimize signal line delay, which optimizes timing and improves performance. The use of Cadence Innovus...

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Bibliographic Details
Main Authors:	Bian Shaoxian, David He, Luan Xiaokun, Jiang Jianfeng, Zhai Feixue, Cai Zhun
Format:	Article
Language:	zho
Published:	National Computer System Engineering Research Institute of China 2019-08-01
Series:	Dianzi Jishu Yingyong
Subjects:	innovus physical implementation secondary placement optimization
Online Access:	http://www.chinaaet.com/article/3000107391

id	doaj-999026a0b9d84d1c82983423edbc1189
record_format	Article
spelling	doaj-999026a0b9d84d1c82983423edbc11892020-11-25T00:34:30ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982019-08-01458485210.16157/j.issn.0258-7998.1998043000107391A physical implementation method based on Innovus to improve chip performanceBian Shaoxian0David He1Luan Xiaokun2Jiang Jianfeng3Zhai Feixue4Cai Zhun5Tianjin Phytium Technology Co.，Ltd.，Changsha 410000，ChinaTianjin Phytium Technology Co.，Ltd.，Changsha 410000，ChinaTianjin Phytium Technology Co.，Ltd.，Changsha 410000，ChinaTianjin Phytium Technology Co.，Ltd.，Changsha 410000，ChinaTianjin Phytium Technology Co.，Ltd.，Changsha 410000，ChinaCadence Design Systems,Inc.，Shanghai 201204，ChinaFor high-performance chip designs with ever-increasing scale and increasing operating frequency, performance has always been the focus and difficulty of physical design. The buffer is inserted to minimize signal line delay, which optimizes timing and improves performance. The use of Cadence Innovus tools to build physical design flows that reduce deviations between steps is described. At the same time, based on this process, a secondary layout optimization method is proposed. The process and method are verified by a high-performance chip design at 16 nm. The example results show that the design performance is greatly improved, and the timing optimization is 85.07%. The flow and method can effectively improve high performance chip performance.http://www.chinaaet.com/article/3000107391innovusphysical implementationsecondary placement optimization
collection	DOAJ
language	zho
format	Article
sources	DOAJ
author	Bian Shaoxian David He Luan Xiaokun Jiang Jianfeng Zhai Feixue Cai Zhun
spellingShingle	Bian Shaoxian David He Luan Xiaokun Jiang Jianfeng Zhai Feixue Cai Zhun A physical implementation method based on Innovus to improve chip performance Dianzi Jishu Yingyong innovus physical implementation secondary placement optimization
author_facet	Bian Shaoxian David He Luan Xiaokun Jiang Jianfeng Zhai Feixue Cai Zhun
author_sort	Bian Shaoxian
title	A physical implementation method based on Innovus to improve chip performance
title_short	A physical implementation method based on Innovus to improve chip performance
title_full	A physical implementation method based on Innovus to improve chip performance
title_fullStr	A physical implementation method based on Innovus to improve chip performance
title_full_unstemmed	A physical implementation method based on Innovus to improve chip performance
title_sort	physical implementation method based on innovus to improve chip performance
publisher	National Computer System Engineering Research Institute of China
series	Dianzi Jishu Yingyong
issn	0258-7998
publishDate	2019-08-01
description	For high-performance chip designs with ever-increasing scale and increasing operating frequency, performance has always been the focus and difficulty of physical design. The buffer is inserted to minimize signal line delay, which optimizes timing and improves performance. The use of Cadence Innovus tools to build physical design flows that reduce deviations between steps is described. At the same time, based on this process, a secondary layout optimization method is proposed. The process and method are verified by a high-performance chip design at 16 nm. The example results show that the design performance is greatly improved, and the timing optimization is 85.07%. The flow and method can effectively improve high performance chip performance.
topic	innovus physical implementation secondary placement optimization
url	http://www.chinaaet.com/article/3000107391
work_keys_str_mv	AT bianshaoxian aphysicalimplementationmethodbasedoninnovustoimprovechipperformance AT davidhe aphysicalimplementationmethodbasedoninnovustoimprovechipperformance AT luanxiaokun aphysicalimplementationmethodbasedoninnovustoimprovechipperformance AT jiangjianfeng aphysicalimplementationmethodbasedoninnovustoimprovechipperformance AT zhaifeixue aphysicalimplementationmethodbasedoninnovustoimprovechipperformance AT caizhun aphysicalimplementationmethodbasedoninnovustoimprovechipperformance AT bianshaoxian physicalimplementationmethodbasedoninnovustoimprovechipperformance AT davidhe physicalimplementationmethodbasedoninnovustoimprovechipperformance AT luanxiaokun physicalimplementationmethodbasedoninnovustoimprovechipperformance AT jiangjianfeng physicalimplementationmethodbasedoninnovustoimprovechipperformance AT zhaifeixue physicalimplementationmethodbasedoninnovustoimprovechipperformance AT caizhun physicalimplementationmethodbasedoninnovustoimprovechipperformance
_version_	1725313039165554688

A physical implementation method based on Innovus to improve chip performance

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