Design and simulation of high-performance 2:1 multiplexer based on side-contacted FED

• Main Authors: Tara Ghafouri, Negin Manavizadeh
• Format: Article
• Language: English
• Published: Elsevier 2021-03-01
• Series: Ain Shams Engineering Journal
• Subjects: Multiplexer design; Side-contacted field-effect diode (S-FED); Noise margin; Power consumption; Switching frequency
• Online Access: http://www.sciencedirect.com/science/article/pii/S209044792030109X

Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high ION/IOFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.