Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical charac...

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Bibliographic Details
Main Authors: Davide Cutaia, Kirsten E. Moselund, Mattias Borg, Heinz Schmid, Lynne Gignac, Chris M. Breslin, Siegfried Karg, Emanuele Uccelli, Heike Riel
Format: Article
Language:English
Published: IEEE 2015-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
heterojunctions
III-V semiconductor materials
nanowires
tunnel diode
tunnel transistor
low-power electronics.
Online Access:https://ieeexplore.ieee.org/document/7001544/

Internet

https://ieeexplore.ieee.org/document/7001544/

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