A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN ac...

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Bibliographic Details
Main Authors: Hasan Irmak, Federico Corradi, Paul Detterer, Nikolaos Alachiotis, Daniel Ziener
Format: Article
Language:English
Published: MDPI AG 2021-08-01
Series:Journal of Low Power Electronics and Applications
Subjects:
FPGA
NN
CNN
SNN
partial reconfiguration
Online Access:https://www.mdpi.com/2079-9268/11/3/32

Internet

https://www.mdpi.com/2079-9268/11/3/32

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