A memory reduced Turbo code decoding architecture design and FPGA implementation
In order to satisfy the high-performance and low-power dissipation requirement in wireless communication, this paper proposes a low storage capacity and low-power dissipation Turbo decoder architecture based on the reverse recalculation and linear estimation by changing the storage method of the for...
Main Authors: | , , , , , |
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Format: | Article |
Language: | zho |
Published: |
National Computer System Engineering Research Institute of China
2019-07-01
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Series: | Dianzi Jishu Yingyong |
Subjects: | |
Online Access: | http://www.chinaaet.com/article/3000106271 |