Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications
Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset ra...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-07-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9268/9/3/21 |