Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal
In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depend...
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| Format: | Article |
| Language: | deu |
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Mirton Publishing House, Timisoara
2006-01-01
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| Series: | Anale: Seria Informatică |
| Online Access: | http://anale-informatica.tibiscus.ro/download/lucrari/4-1-23-Timis.pdf |