Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal
In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depend...
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Mirton Publishing House, Timisoara
2006-01-01
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| Series: | Anale: Seria Informatică |
| Online Access: | http://anale-informatica.tibiscus.ro/download/lucrari/4-1-23-Timis.pdf |
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doaj-a536d4bd2eb94d55a6eb56edba1cf4e22020-11-24T23:47:56ZdeuMirton Publishing House, TimisoaraAnale: Seria Informatică1583-71652065-74712006-01-0141237242Output Width Signal Control In Asynchronous Digital Systems Using External Clock SignalMihai TimişIn present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods, like using a RC group system, a monostabil system in design of the asynchronous digital system or using an external clock signal, CK. In this paper will be used an external clock signal, CK.http://anale-informatica.tibiscus.ro/download/lucrari/4-1-23-Timis.pdf |
| collection |
DOAJ |
| language |
deu |
| format |
Article |
| sources |
DOAJ |
| author |
Mihai Timiş |
| spellingShingle |
Mihai Timiş Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal Anale: Seria Informatică |
| author_facet |
Mihai Timiş |
| author_sort |
Mihai Timiş |
| title |
Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal |
| title_short |
Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal |
| title_full |
Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal |
| title_fullStr |
Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal |
| title_full_unstemmed |
Output Width Signal Control In Asynchronous Digital Systems Using External Clock Signal |
| title_sort |
output width signal control in asynchronous digital systems using external clock signal |
| publisher |
Mirton Publishing House, Timisoara |
| series |
Anale: Seria Informatică |
| issn |
1583-7165 2065-7471 |
| publishDate |
2006-01-01 |
| description |
In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods, like using a RC group system, a monostabil system in design of the asynchronous digital system or using an external clock signal, CK. In this paper will be used an external clock signal, CK. |
| url |
http://anale-informatica.tibiscus.ro/download/lucrari/4-1-23-Timis.pdf |
| work_keys_str_mv |
AT mihaitimis outputwidthsignalcontrolinasynchronousdigitalsystemsusingexternalclocksignal |
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1725488068299849728 |