PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT) is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody). Simulation...

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Bibliographic Details
Main Authors: T. Tharaneeswaran, S. Ramasamy
Format: Article
Language:English
Published: ICT Academy of Tamil Nadu 2012-06-01
Series:ICTACT Journal on Communication Technology
Subjects:
Leakage currents
current comparator
charge pump
VLSI
LPMT
Online Access:http://ictactjournals.in/paper/IJCT_Vol3_Iss2_P7_557_562.pdf

Internet

http://ictactjournals.in/paper/IJCT_Vol3_Iss2_P7_557_562.pdf

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