A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

This paper presents a multiply-accumulate (MAC) unit that enables a dual-mode truncation error compensation (TEC) scheme based on a fixed-width Booth multiplier (FWBM) for convolutional neural network (CNN) inference operations. The proposed tailored TEC schemes of Modes 1 and 2 can achieve high MAC...

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Bibliographic Details
Main Authors: Song-Nien Tang, Yu-Shin Han
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Multiply-accumulate
MAC
2D convolution
convolutional neural network
CNN
accelerator
Online Access:https://ieeexplore.ieee.org/document/9270007/

Internet

https://ieeexplore.ieee.org/document/9270007/

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