Low power frequency doubler
A low power frequency doubler circuit that only requires standard CMOS logic gates and on-chip passive components is proposed. The proposed circuit is shown to be compact and has been validated with FPGA implementation. The proposed circuit is found to be robust to wide frequency range and supply vo...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
KeAi Communications Co., Ltd.
2020-01-01
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| Series: | Solid State Electronics Letters |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2589208820300260 |