Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

This work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with the voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) cha...

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Bibliographic Details
Main Authors: Jiri Petrzela, Roman Sotner
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Analogue binary memory
bifurcation diagram
electronic tuning
chaos
Lyapunov exponent
piecewise-linear (PWL) resistors
Online Access:https://ieeexplore.ieee.org/document/9244145/

Internet

https://ieeexplore.ieee.org/document/9244145/

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