ADVANCED SCHEDULER FOR COOPERATIVE EXECUTION OF THREADS ON MULTI-CORE SYSTEM

ADVANCED SCHEDULER FOR COOPERATIVE EXECUTION OF THREADS ON MULTI-CORE SYSTEM

Three architectures of the cooperative thread scheduler in a multithreaded application that is executed on a multi-core system are considered. Architecture A0 is based on the synchronization and scheduling facilities, which are provided by the operating system. Architecture A1 introduces a new synch...

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Bibliographic Details
Main Authors: O. N. Karasik, A. A. Prihozhy
Format: Article
Language:English
Published: Belarusian National Technical University 2017-05-01
Series:Sistemnyj Analiz i Prikladnaâ Informatika
Subjects:
three architectures of the cooperative thread scheduler in a multithreaded application that is executed on a multi-core system are considered. architecture a0 is based on the synchronization and scheduling facilities, which are provided by the operating system. architecture a1 introduces a new synchronization primitive and a single queue of the blocked threads in the scheduler, which reduces the interaction activity between the threads and operating system, and significantly speed up the processes of blocking and unblocking the threads. architecture a2 replaces the single queue of blocked threads with dedicated queues, one for each of the synchronizing primitives, extends the number of internal states of the primitive, reduces the inter- dependence of the scheduling threads, and further significantly speeds up the processes of blocking and unblocking the threads. all scheduler architectures are implemented on windows operating systems and based on the user mode scheduling. important experimental results are obtained for multithreaded applications that implement two blocked parallel algorithms of solving the linear algebraic equation systems by the gaussian elimination. the algorithms differ in the way of the data distribution among threads and by the thread synchronization models. the number of threads varied from 32 to 7936. architecture a1 shows the acceleration of up to 8.65% and the architecture a2 shows the acceleration of up to 11.98% compared to a0 architecture for the blocked parallel algorithms computing the triangular form and performing the back substitution. on the back substitution stage of the algorithms, architecture a1 gives the acceleration of up to 125%, and architecture a2 gives the acceleration of up to 413% compared to architecture a0. the experiments clearly show that the proposed architectures, a1 and a2 outperform a0 depending on the number of thread blocking and unblocking operations, which happen during the execution of multi-threaded applications. the conducted computational experiments demonstrate the improvement of parameters of multithreaded applications on a heterogeneous multi-core system due the proposed advanced versions of the thread scheduler.
Online Access:https://sapi.bntu.by/jour/article/view/144

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