On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology

On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology

A new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell. Merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process. The scaled gate length enables the SAN cell be erased by band-to-band hot hole. For multiple-time-programming operatio...

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Bibliographic Details
Main Authors: Po-Yen Lin, Yu-Lun Chiu, Yuh-Te Sung, Jim Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong Jung Lin
Format: Article
Language:English
Published: IEEE 2015-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Charge Pumping
Nonvolatile Memory
Reliability
Self -Recovery
Online Access:https://ieeexplore.ieee.org/document/7234841/

Internet

https://ieeexplore.ieee.org/document/7234841/

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