G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA
This paper presents a novel architecture for ternary content-addressable memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a memory element and...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2017-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8049445/ |