Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W<sub>eff</sub> per existing footp...

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Main Authors:	Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu
Format:	Article
Language:	English
Published:	IEEE 2019-01-01
Series:	IEEE Journal of the Electron Devices Society
Subjects:	Gate all around junctionless nanosheet multi gate stacked FET
Online Access:	https://ieeexplore.ieee.org/document/8894119/

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record_format	Article
spelling	doaj-beb36e72cf9342389ae6efc9c2f0a9f82021-03-29T18:50:21ZengIEEEIEEE Journal of the Electron Devices Society2168-67342019-01-0171133113910.1109/JEDS.2019.29521508894119Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect TransistorsMeng-Ju Tsai0Kang-Hui Peng1Chong-Jhe Sun2Siao-Cheng Yan3Chieng-Chung Hsu4Yu-Ru Lin5Yu-Hsien Lin6https://orcid.org/0000-0001-7570-7949Yung-Chun Wu7https://orcid.org/0000-0001-9409-6792Department of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Electronic Engineering, National United University, Miaoli, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanPresent work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W<sub>eff</sub> per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (> 10<sup>8</sup>), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices.https://ieeexplore.ieee.org/document/8894119/Gate all aroundjunctionlessnanosheetmulti gatestacked FET
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Meng-Ju Tsai Kang-Hui Peng Chong-Jhe Sun Siao-Cheng Yan Chieng-Chung Hsu Yu-Ru Lin Yu-Hsien Lin Yung-Chun Wu
spellingShingle	Meng-Ju Tsai Kang-Hui Peng Chong-Jhe Sun Siao-Cheng Yan Chieng-Chung Hsu Yu-Ru Lin Yu-Hsien Lin Yung-Chun Wu Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors IEEE Journal of the Electron Devices Society Gate all around junctionless nanosheet multi gate stacked FET
author_facet	Meng-Ju Tsai Kang-Hui Peng Chong-Jhe Sun Siao-Cheng Yan Chieng-Chung Hsu Yu-Ru Lin Yu-Hsien Lin Yung-Chun Wu
author_sort	Meng-Ju Tsai
title	Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
title_short	Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
title_full	Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
title_fullStr	Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
title_full_unstemmed	Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
title_sort	fabrication and characterization of stacked poly-si nanosheet with gate-all-around and multi-gate junctionless field effect transistors
publisher	IEEE
series	IEEE Journal of the Electron Devices Society
issn	2168-6734
publishDate	2019-01-01
description	Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W<sub>eff</sub> per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (> 10<sup>8</sup>), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices.
topic	Gate all around junctionless nanosheet multi gate stacked FET
url	https://ieeexplore.ieee.org/document/8894119/
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Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

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