A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

We consider practical hardware implementation of polar decoders. To reduce latency due to the serial nature of successive cancellation, existing optimizations improve parallelism with two approaches, i.e., multi-bit decision or reduced path splitting. In this paper, we combine the two procedures int...

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Bibliographic Details
Main Authors: Huazi Zhang, Jiajie Tong, Rong Li, Pengcheng Qiu, Yourui Huangfu, Chen Xu, Xianbin Wang, Jun Wang
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Channel coding
decoding
hardware
low latency
Online Access:https://ieeexplore.ieee.org/document/8573887/

Internet

https://ieeexplore.ieee.org/document/8573887/

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