Implementation of NoC on FPGA with Area and Power Optimization
On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size, speed, power and area. The goal of working wa...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
European Alliance for Innovation (EAI)
2019-03-01
|
| Series: | EAI Endorsed Transactions on Context-aware Systems and Applications |
| Subjects: | |
| Online Access: | https://eudl.eu/pdf/10.4108/eai.23-5-2019.158953 |